AVRs are generally classified into four broad groups:

• tinyAVR -- the ATtiny series
  • 8-32-pin package
  • 1-8 kB program memory
  • Limited peripheral set

• megaAVR -- the ATmega series
  • 28-100-pin package
  • 4-256 kB program memory
  • Extended instruction set (Multiply instructions and instructions for handling larger program memories)
  • Extensive peripheral set

• XMEGA -- the ATxmega series
  • 44-64-100-pin package (A4, A3, A1)
  • 16-384 kB program memory
  • Extended performance features, such as DMA, "Event System", and cryptography support.
  • Extensive peripheral set with DACs

• Application specific AVR
  • megaAVRs with special features not found on the other members of the AVR family, such as USB controller, LCD controller, advanced PWM, CAN etc.
  • FPSLIC (Field Programmable System Level Integrated Circuit), an AVR core on-die with an FPGA. The FPSLIC uses SRAM for the AVR program code, unlike all other AVRs. Partly due to the relative speed difference between SRAM and flash, the AVR core in the FPSLIC can run at up to 50MHz.

Current AVRs offer a wide range of features:

• Internal, Self-Programmable Instruction Flash Memory up to 256 K
• Multiple Internal Oscillators
• Multifunction, Bi-directional General Purpose I/O ports with configurable, built-in pull-up resistors
  • In-System Programmable using ISP, JTAG, or High Voltage methods
  • Optional Boot Code Section with Independent Lock Bits for Protection
• On chip debugging (OCD) support through JTAG or debugWIRE on most devices
  • The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on GPIOs. These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP. By default, AVRs with JTAG come with the JTAG interface enabled.
  • debugWIRE uses the /RESET pin as a bi-directional communication channel to access on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin. debugWIRE can only be enabled using ISP or HVSP. Once enabled, it can only be disabled via the debugWIRE interface.
• Internal SRAM up to 8 K
• External 64KB little endian data space on certain models, including the Mega8515 and Mega162.
• Internal Data EEPROM up to 4 kB
  • The external data space is overlaid with the internal data space, such that the full 64KB address space does not appear on the external bus. An accesses to e.g. address 0100₁₆ will access internal RAM, not the external bus.
  • In certain members of the XMEGA series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16MB of data memory to be directly addressed.
  • AVR's generally do not support executing code from external memory. Some ASSP's using the AVR code do support external program memory.
• 8-Bit and 16-Bit Timers
  • PWM output (Dead time generator on some devices)
  • Input capture
• 10 or 12-Bit A/D Converters, with multiplex of up to 16 channels
• 12-bit D/A Converters
• Analog Comparators
• A variety of serial interfaces, including
  • Synchronous/Asynchronous Serial Peripherals (UART/USART) (used with RS-232, RS-485, and more)
  • Serial Peripheral Interface Bus (SPI)
  • I²C Compatible Two-Wire Interface (TWI)
  • Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
• USB Controller Support
• Watchdog Timer (WDT)
• Lighting and motor control (PWM Specific) Controller models
• Multiple Power-Saving Sleep Modes
• CAN Controller Support
• Brownout Detection
  • Proper High-speed hardware & Hub controller with embedded AVR.
  • Also freely available low-speed (HID) software emulation
• LCD Controller Support
• Ethernet Controller Support
• Low-voltage Devices Operating Down to 1.8v
• picoPower Devices
• Fast Cryptography support for AES and DES
• DMA controllers and "Event System" peripheral communication.