The AVR is a Modified Harvard architecture machine with program and data stored in separate physical memory systems that appear in different address spaces but having the ability to read data items from program memory using special instructions.

AVRs are generally classified into four broad groups:

• tinyAVRs
  • 8-32-pin package
  • 1-8 kB program memory
  • Limited peripheral set

• megaAVRs
  • 28-100-pin package
  • 4-256 kB program memory
  • Extended instruction set (Multiply instructions and instructions for handling larger program memories)
  • Extensive peripheral set

• XMEGA
  • 44-100-pin package
  • 16-256 kB program memory
  • Extended performance features, such as DMA, "Event System", and cryptography support.
  • Extensive peripheral set with DACs

• Application specific AVRs
  • megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc.
  • FPSLIC (Field Programmable System Level Integrated Circuit), an AVR core on-die with an FPGA. The FPSLIC uses SRAM for the AVR program code, unlike all other AVRs. Partly due to the relative speed difference between SRAM and flash, the AVR core in the FPSLIC can run at up to 50MHz.

Device Architecture

Data RAM

Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need for external memory. Some devices have an external bus to allow adding additional data memory or memory-mapped devices.

Internal Data Memory

The data address space consists of the register file, I/O registers, and SRAM. The AVRs have 32 single-byte registers and are classified as 8-bit RISC devices.

Program Memory (Flash)

Program instructions are stored in non-volatile Flash memory. Although they are 8-bit MCUs, each instruction takes one or two 16-bit words. The size of the program memory is occasionally indicated in the naming of the device itself (e.g., the ATmega64x line has 64 kB of Flash). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash.

Internal Registers

In most variants of the AVR architecture, the working registers are mapped in as the first 32 memory addresses (0000₁₆-001F₁₆) followed by the 64 I/O registers (0020₁₆-005F₁₆).

Actual SRAM starts after these register sections (address 0060₁₆). Note that the I/O register space may be larger on some more extensive devices, in which case the memory mapped I/O registers will occupy a portion of the SRAM address space.

Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM.

In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000₁₆-0FFF₁₆). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space which can be used optionally for mapping the internal EEPROM to the data address space (1000₁₆-1FFF₁₆). The actual SRAM is located after these ranges, starting at 2000₁₆.

EEPROM

Almost all AVR microcontrollers have internal Electrically Erasable Programmable Read Only Memory (EEPROM) for semi-permanent data storage. Like Flash memory, EEPROM can maintain its contents when electrical power is removed.

In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions which makes EEPROM access much slower than other internal RAM.

However, some devices in the SecureAVR (AT90SC) family uses a special EEPROM mapping to the data or program memory depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space.

Since the number of writes to EEPROM is not unlimited - Atmel specifies 100,000 write cycles in their datasheets - a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if contents need to be changed.

Program Execution

Atmel's AVRs have a three stage, single level pipeline design. This means the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers.

The AVR family of processors were designed with the efficient execution of compiled C code in mind and has several built-in pointers for the task.

Instruction Set

Main article: Atmel AVR instruction set

The AVR Instruction Set is more orthogonal than most eight-bit microcontrollers, in particular the PIC microcontrollers with which AVR competes today. However, it is not completely regular:

• Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31.
• Pointer registers X, Y, and Z have addressing capabilities that are different from each other.
• I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63.
• CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note that CLR is pseudo-op for EOR R, R; and SER is short for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.)

The mostly-regular instruction set makes programming it using C (or even Pascal) compilers fairly straightforward. In fact, Atmel solicited input from major developers of compilers for small microcontrollers, to determine the instruction set features that were most useful in a compiler for high-level languages.

MCU Speed

The AVR line can normally support clock speeds from 0-20 MHz, with some devices reaching 32 MHz. Lower powered operation usually requires a reduced clock speed. All recent (Tiny and Mega, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Some AVRs also have a system clock prescaler that can divide down the system clock by up to 256. This prescaler can be reconfigured by software during run-time, allowing to optimize clock speed. Since all operations (excluding literals) on registers R0 - R31 are single cycle, the AVR can achieve up to 1MIPS per MHz. Loads and stores to/from memory take 2 cycles, branching takes 3 cycles.

Development

AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core but with different peripheral and memory combinations. Compatibility amongst chips is fairly good.

The AVRs are sold under various names that share the same basic core but with different peripheral and memory combinations. Compatibility amongst chips is fairly good. AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software.