This project implements an 8 bit controller that is compatible with Atmel's AVR architecture, using VHDL (Very High speed integrated circuits Hardware Description Language). pAVR is an 8 bit controller fully compatible with Atmel's AVR architecture. pAVR stands for "pipelined AVR". You can also find here the core pAVR sources, some tests and results of synthesis on Xilinx Spartan 3 FPGA.
pAVR is not a specific controller of the AVR family, but rather a maximally featured AVR. It is configurable enough to be able to simulate most AVR family controllers. The goal was to obtain an AVR processor that is as powerful as possible (in terms of MIPS), with a work budget of about 6 months*man. AVR is about 3x faster than the original core, if built with the same technology.
The sources are modularized. They are written starting from a set of common-sense conventions (the process splitting strategy, signals naming, etc)., so that pAVR is quite an easily maintainable design. A comprehensive documentation is provided. Extensive testing was carried out.
Features
- 6 pipeline stages
- 1 clock/instruction for most instructions
- estimated clock frequency: ~50 MHz & 0.5 um; assuming that Atmel's core runs at 15 MHz & 0.5 um. That's ~3x Atmel original core's performance.
- estimated MIPS at 50 MHz: 28 MIPS (typical), 50 MIPS (peak). That's ~3x Atmel original core's performance. At 15 MHz, Atmel's core has 10 MIPS typical, and 15 MIPS peak.
- CPI (clocks per instruction): 1.7 clocks/instruction (typical), 1 clock/instruction (peak). That's ~0.75x (typical), 1.00x (peak) Atmel original core's performance.
- up to 32 interrupt sources. Each interrupt has programmable priority and jump address.
- heavily parameterized design that permits flexible costumization
- pAVR architecture is rather computational-friendly than control-friendly. Jumps, branches, skips, calls and returns are relatively expansive in terms of clocks. A branch prediction scheme and a smarter return procedure might be considered as upgrades.
Microcontroller core compatible with one used in AT mega 103 and written in VHDL. It has the same instruction timing and the same instruction set (with a few exceptions).
Features
• Core features:
– 32 x 8 general purpose registers
– Twenty three interrupt vectors
– Supports up to 128 Kb of program and up to 64 Kb of data memory
• Peripheral features:
– Programmable UART
– Two 8-bit Timer/Counters with separate prescalers and PWM
– Eight external interrupt sources
– Two parallel ports
Status
The core was tested with several ASM and C programs. It was implemented in Altera EPF10K50ETC144-3 device and tested with AVR port of uC/OS-II The Real-Time Kernel, written by Ole Saether.(I used special version of the design with external SRAM for both program and data memories).
This is a Atmel AVR ATtiny261/461/861 compatible core. It should be (more or less) fully code compliant, but it is not clock-cycle compliant. The reason it was developed was to have a simple core to develop C-code to. The implementation is rather strait forward without any pipelining. One reason was also to see how hard it was to implement a standard mcu in vhdl and make it run on gcc-generated code. The implementation is a bit quick-n-dirty, I spent about 15h coding the core and about 15h to writing test bench and simulate the core. Please note, you should not use the AVRStudio for development to this core, the files generated by AVRStudio is compatible with the core, BUT, if you don't buy the mcu from Atmel, you shouldn't use their software!
The test bench uses code (C and Asm) compiled only with the help of gnu-tools.
Info
Status
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